Employing an ultrathin dielectric composed of a 4-nanometer-thick layer of lanthanum aluminate with an ultrathin, 0.5-nanometer layer of aluminum oxide, Purdue University's nanowire transistor of indium-gallium-arsenide (IGA) reaches an important milestone of a 20 nm gate size.
Currently Intel Corp. (INTC) uses a 22 nm process for its Ivy Bridge silicon-based transistors.
The new IGA transistor, like Intel's fin shaped 3D transistors, employs a three-dimensional gate design, but it takes it even a step farther, creating a bizarre stackable design of triple-tapering nanowires that looks like a tiny pine tree.
Peide "Peter" Ye, a professor of electrical and computer engineering at Purdue University, has an interesting name for his new device -- "the 4D transistor". He comments, "A one-story house can hold so many people, but more floors, more people, and it's the same thing with transistors. Stacking them results in more current and much faster operation for high-speed computing. This adds a whole new dimension, so I call them 4-D."
He says the superior electron mobility of the new transistor allowed the novel design, and may allow even more ambitious successors.
The new work was published in a pair of papers [PDF] to be presented at the International Electron Devices Meeting on Dec. 8-12 in San Francisco.
Currently the silicon chipmaking industry is in an uncertain state. 14 nm chips are expected for 2015, while researchers hope to shrink to 10 nm by 2018. But past 14 nm, leakage in current "high K" dielectrics will become to severe for the transistor to operate; hence to stay on course for 2018 researchers must race to discover new dielectrics.
Squeezing past 10 nm will be even trickier, as it's pushing the boundaries of the already strained optical lithography techniques. Advanced techniques like self-assembly or mechanical manipulation of atoms may prove crucial at features sizes below 10 nm.
Sources: Purdue, Eurekalert
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